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Back*.lck # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: merged pull request synth_mages/MK_VCO#3 created pull request synth_mages/MK_SEQ#1 Binary files /dev/null and b/sr1_full.png differ aac0a4a5b4 Notes from debugging More notes More notes Schematics/schematic_bugs_v1.txt | 2 pin Molex connector 2.54 mm spacing 2 pin Molex connector 2.54 mm spacing