3
1
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LFCSP, exposed pad, thermal vias (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-12-11/ Infineon SO package 20pin without exposed pad (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-20-85/ Infineon SO package 20pin, exposed pad - Ref http://pdfserv.maximintegrated.com/land_patterns/90-0349.PDF DFN, 10 Pin (www.allegromicro.com/~/media/Files/Datasheets/A4952-3-Datasheet.ashx?la=en#page=10), generated with kicad-footprint-generator Hirose DF11 through hole, DF63R-5P-3.96DSA, 5 Pins (https://www.molex.com/pdm_docs/sd/009652028_sd.pdf), generated with.

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