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Library Notes from debugging Clock POT is the two keybeds in storage; decipher key matrix, work out either MC or dumb resistor array to output correct volts for each stage? Latest commits for file Panels/title_test.stl STLs, 10hp version, others schematics Replaced accidentally dropped Fine tuning hole. Latest commits for file Schematics/SynthMages.pretty/Alpha.

• 7.19917 3.46694 19.9405 facet normal 0.100183.
• -8.116212e-001 3.540118e-001 facet normal.

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