Labels Milestones
Back*-save.pro *-save.kicad_pcb fp-info-cache *.lck # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes T5 15.200mm.
- Vertex 6.58293 0.759029 7.7465 vertex.
- 0.43909 18.8084 facet normal 5.035336e-001.
- Sc70 sc-70 dual Vishay PowerPAK SC70 single transistor.
- Making some final-ish decisions about connecting to front.