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Condition "A.isPlated() && B.Type == A.Type")) # 4-layer condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'" condition "A.Net != B.Net" (condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'" (condition "A.Net != B.Net" (condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track'" condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'track'" ; DRILL file {KiCad 5.1.10-88a1d61d58~90~ubuntu20.04.1} date Thu Aug 12 15:59:21 2021 ac58a9eaed checkpoint after roughing out middle PCB Move LED resistors next to transistors to save on panel wires More traces and vias, and net links Schematics/Unseen Servant/fp-info-cache | 1 | Conn_01x07 | \*(optional) SIP socket, 2.54 mm, 1x10 Pin socket, 2.54 mm, 1x10 | | C2, C5, C6, C8, C9 D1, D2, D3, D4, D5, D8, D9, D10 | 8 "active_layer_preset": "All Copper Layers", re-re-remove the mysterious extra trace.

From 057198b8de00d90dc9311b86f496b649dca09ec0 Mon Sep 17 00:00:00.
Hole M2, height 5, Wuerth.

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