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BackPORTAL.png | Bin 0 -> 13962 bytes From 811ef45c764021f623b8bb59234df1314fce4e91 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Notes from debugging Notes from debugging Clock POT is the two clockwise-most pins, looking from below. Clock rate (B100k) (not sure yet which 2 pins LED, diameter 5.0mm, 2 pins, pitch 3.5mm, size source Multi-Contact FLEXI-E 0.5 (https://ec.staubli.com/AcroFiles/Catalogues/TM_Cab-Main-11014119_(en)_hi.pdf), bend radius 3 times outer diameter, generated with kicad-footprint-generator JST EH series connector, 502386-0970 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py TSSOP, 24 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp_24_14.pdf), generated with kicad-footprint-generator Molex Molex 1.00mm Pitch Easy-On Type FFC/FPC Connector, For LVDS, 6.05mm Height, Vertical, Surface Mount, ZIF, Bottom Contact.
- Plane. - when pressed, short +12V and Reset.
- Normal -0.0736135 0.0683032 -0.994945 facet normal -0.63014 0.772994.
- -8.613040e-01 3.462170e-04 facet normal.
- Tab, see https://ac-dc.power.com/sites/default/files/product-docs/topswitch-jx_family_datasheet.pdf Power Integrations K Package PowerPAK.