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BackWithout needing a separate file or files, that is intentionally submitted to JLCPCB on 20240124 63579cf959 Add notes about UX component wiring 9f9f6acf76f746b4755da71c07bb656091774052 SMT updates 13c8bcac477b612d33e1b1cfe89a6f9adc0a8935 Adding SynthMages footprint library 4579d541a87627c8f72d8a9f964497261ff44987 More random files 7e24b3de83 Notes from debugging Clock POT is too small for film; is film needed? - Fix R25/R1 connection - One potentiometer for internal clock rate. - One SPDT switch to set output voltages. (10) One potentiometer per step, to set output voltages. (10) One potentiometer for internal clock rate. Arrasta Playbook REP: repique CAX: caixa MSD: mid surdo (sometimes MS1, MS2, etc, if multiple measures or variations) BSD: back surdo (L for low, H for high) R/L: accented note (right/left hand suggested)