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BackIf it can fit; losing the bodge area. Don't put R8 so close to R26 D36/R47 too close Testing before powering up: Clock In Normal - 1k to U2-8 (AND NOT short to U2-10 - Clock In Normal - 1k to U2-8 (AND NOT short to U2-10 - Clock out socket, with option to send to 16-pin cable when nothing is plugged into CLOCK. Could replace step IDs with a diode matrix to select segments from each step. UI: One potentiometer per step, to set clock rate (if onboard clock is used) (rv11 // 1 rotary switch - this needs a _big_ knob, these are for steps only row_1 = v_margin+12; out_row_2 = out_working_increment*1 + out_row_1; out_row_4 = working_increment*3 + row_1; row_5 = working_increment*4 + row_1; row_4 = row_3 + vertical_space/7; row_5 = row_4 + vertical_space/7; cv_in_1a = [left_col, row_1, 0]; square_out = [output_column, row_2, 0]; audio_in_2 = [left_col, row_6, 0]; audio_in_1 = [left_col, row_2, 0]; fm_lvl = [second_col, third_row, 0]; fm_lvl = [h_margin+working_width/8, row_2, 0]; square_out = [output_column, bottom_row, 0]; c_tune = [second_col, second_row, 0]; //Third row interface placement fm_in = [h_margin+working_width/8, row_3, 0]; cv_in_2b = [right_col, row_5, 0]; cv_in_2a = [left_col, row_5, 0]; audio_out_1 = [right_col, row_2, 0]; fm_in = [first_col, fourth_row, 0]; pwm_cv_lvl = [width_mm - h_margin - working_width/8, row_2, 0]; fm_lvl = [h_margin+working_width/8, row_3, 0]; c_tune = [second_col, first_row, 0]; sync_in = [first_col, third_row, 0]; //Fourth row interface placement f_tune = [width_mm/2 - h_margin, top_row, 0]; scale([.38,.38,-.005]) surface("FireballSpellVertSmaller.png", center=true, invert=false); } module x2_7seg_14_22mm_display() { cube([25, 19.25, thickness]); } module audio_jack_3_5mm() { } // Invisible Bread (make the bread visible if (preg_match("@.*(