new_footprints #5
8 changed files with 39975 additions and 4347 deletions
102
Fireball/Fireball.kicad_dru
Normal file
102
Fireball/Fireball.kicad_dru
Normal file
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@ -0,0 +1,102 @@
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(version 1)
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#Kicad 7
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# 2-layer, 1oz copper
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(rule "Minimum Trace Width (outer layer)"
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(constraint track_width (min 5mil))
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(layer outer)
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(condition "A.Type == 'track'"))
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(rule "Minimum Trace Spacing (outer layer)"
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(constraint clearance (min 5mil))
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(layer outer)
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(condition "A.Type == 'track' && B.Type == A.Type"))
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# 4-layer
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(rule "Minimum Trace Width and Spacing (inner layer)"
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(constraint track_width (min 3.5mil))
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(layer inner)
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(condition "A.Type == 'track'"))
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(rule "Minimum Trace Spacing (inner layer)"
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(constraint clearance (min 3.5mil))
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(layer inner)
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(condition "A.Type == 'track' && B.Type == A.Type"))
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# silkscreen (Kicad 7 only)
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(rule "Minimum Text"
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(constraint text_thickness (min 0.15mm))
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(constraint text_height (min 1mm))
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(layer "?.Silkscreen"))
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(rule "Pad to Silkscreen"
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(constraint silk_clearance (min 0.15mm))
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(layer outer)
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(condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'graphic')"))
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# edge clearance
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(rule "Trace to Outline"
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(constraint edge_clearance (min 0.2mm))
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(condition "A.Type == 'track'"))
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# This would override board outline and milled areas
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#(rule "Trace to V-Cut"
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# (constraint clearance (min 0.4mm))
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# (condition "A.Type == 'track' && B.Layer == 'Edge.Cuts'"))
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# drill/hole size
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(rule "drill hole size (mechanical)"
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(constraint hole_size (min 0.2mm) (max 6.3mm)))
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(rule "Minimum Via Hole Size"
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(constraint hole_size (min 0.2mm))
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(condition "A.Type == 'via'"))
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(rule "Minimum Via Diameter"
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(constraint via_diameter (min 0.45mm))
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(condition "A.Type == 'via'"))
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(rule "PTH Hole Size"
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(constraint hole_size (min 0.2mm) (max 6.35mm))
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(condition "A.isPlated()"))
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(rule "Minimum Non-plated Hole Size"
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(constraint hole_size (min 0.5mm))
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(condition "A.Type == 'pad' && !A.isPlated()"))
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(rule "Minimum Castellated Hole Size"
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(constraint hole_size (min 0.6mm))
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(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'"))
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# clearance
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(rule "hole to hole clearance (different nets)"
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(constraint hole_to_hole (min 0.5mm))
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(condition "A.Net != B.Net"))
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(rule "via to track clearance"
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(constraint hole_clearance (min 0.254mm))
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(condition "A.Type == 'via' && B.Type == 'track'"))
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(rule "via to via clearance (same nets)"
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(constraint hole_to_hole (min 0.254mm))
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(condition "A.Type == 'via' && B.Type == A.Type && A.Net == B.Net"))
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(rule "pad to pad clearance (with hole, different nets)"
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(constraint hole_to_hole (min 0.5mm))
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(condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net"))
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(rule "pad to pad clearance (without hole, different nets)"
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(constraint clearance (min 0.127mm))
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(condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net"))
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(rule "NPTH to Track clearance)"
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(constraint hole_clearance (min 0.254mm))
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(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track'"))
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(rule "PTH to Track clearance)"
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(constraint hole_clearance (min 0.33mm))
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(condition "A.isPlated() && B.Type == 'track'"))
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(rule "Pad to Track clearance)"
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(constraint clearance (min 0.2mm))
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(condition "A.isPlated() && B.Type == 'track'"))
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File diff suppressed because it is too large
Load diff
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@ -123,8 +123,8 @@
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"min_microvia_drill": 0.09999999999999999,
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"min_resolved_spokes": 2,
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"min_silk_clearance": 0.049999999999999996,
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"min_text_height": 0.7999999999999999,
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"min_text_thickness": 0.08,
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"min_text_height": 1.0,
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"min_text_thickness": 0.153,
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"min_through_hole_diameter": 0.3,
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"min_track_width": 0.19999999999999998,
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"min_via_annular_width": 0.08,
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102
Fireball/Fireball_panel.kicad_dru
Normal file
102
Fireball/Fireball_panel.kicad_dru
Normal file
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@ -0,0 +1,102 @@
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(version 1)
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#Kicad 7
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# 2-layer, 1oz copper
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(rule "Minimum Trace Width (outer layer)"
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(constraint track_width (min 5mil))
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||||
(layer outer)
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(condition "A.Type == 'track'"))
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(rule "Minimum Trace Spacing (outer layer)"
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(constraint clearance (min 5mil))
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(layer outer)
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(condition "A.Type == 'track' && B.Type == A.Type"))
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# 4-layer
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(rule "Minimum Trace Width and Spacing (inner layer)"
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(constraint track_width (min 3.5mil))
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(layer inner)
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(condition "A.Type == 'track'"))
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(rule "Minimum Trace Spacing (inner layer)"
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(constraint clearance (min 3.5mil))
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(layer inner)
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(condition "A.Type == 'track' && B.Type == A.Type"))
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# silkscreen (Kicad 7 only)
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(rule "Minimum Text"
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(constraint text_thickness (min 0.15mm))
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(constraint text_height (min 1mm))
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(layer "?.Silkscreen"))
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(rule "Pad to Silkscreen"
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(constraint silk_clearance (min 0.15mm))
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(layer outer)
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(condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'graphic')"))
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# edge clearance
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(rule "Trace to Outline"
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(constraint edge_clearance (min 0.2mm))
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(condition "A.Type == 'track'"))
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# This would override board outline and milled areas
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#(rule "Trace to V-Cut"
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# (constraint clearance (min 0.4mm))
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# (condition "A.Type == 'track' && B.Layer == 'Edge.Cuts'"))
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# drill/hole size
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(rule "drill hole size (mechanical)"
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(constraint hole_size (min 0.2mm) (max 6.3mm)))
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(rule "Minimum Via Hole Size"
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(constraint hole_size (min 0.2mm))
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(condition "A.Type == 'via'"))
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(rule "Minimum Via Diameter"
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(constraint via_diameter (min 0.45mm))
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(condition "A.Type == 'via'"))
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|
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(rule "PTH Hole Size"
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(constraint hole_size (min 0.2mm) (max 6.35mm))
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(condition "A.isPlated()"))
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(rule "Minimum Non-plated Hole Size"
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(constraint hole_size (min 0.5mm))
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(condition "A.Type == 'pad' && !A.isPlated()"))
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(rule "Minimum Castellated Hole Size"
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(constraint hole_size (min 0.6mm))
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(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'"))
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# clearance
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(rule "hole to hole clearance (different nets)"
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(constraint hole_to_hole (min 0.5mm))
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(condition "A.Net != B.Net"))
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(rule "via to track clearance"
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(constraint hole_clearance (min 0.254mm))
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(condition "A.Type == 'via' && B.Type == 'track'"))
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(rule "via to via clearance (same nets)"
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(constraint hole_to_hole (min 0.254mm))
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(condition "A.Type == 'via' && B.Type == A.Type && A.Net == B.Net"))
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(rule "pad to pad clearance (with hole, different nets)"
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(constraint hole_to_hole (min 0.5mm))
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(condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net"))
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(rule "pad to pad clearance (without hole, different nets)"
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(constraint clearance (min 0.127mm))
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(condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net"))
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(rule "NPTH to Track clearance)"
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(constraint hole_clearance (min 0.254mm))
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(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track'"))
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(rule "PTH to Track clearance)"
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(constraint hole_clearance (min 0.33mm))
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(condition "A.isPlated() && B.Type == 'track'"))
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(rule "Pad to Track clearance)"
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(constraint clearance (min 0.2mm))
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(condition "A.isPlated() && B.Type == 'track'"))
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File diff suppressed because it is too large
Load diff
77
Fireball/Fireball_panel.kicad_prl
Normal file
77
Fireball/Fireball_panel.kicad_prl
Normal file
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@ -0,0 +1,77 @@
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{
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"board": {
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"active_layer": 37,
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"active_layer_preset": "All Layers",
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"auto_track_width": true,
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"hidden_netclasses": [],
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"hidden_nets": [],
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"high_contrast_mode": 0,
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"net_color_mode": 1,
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"opacity": {
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"images": 0.6,
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"pads": 1.0,
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"tracks": 1.0,
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"vias": 1.0,
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"zones": 0.6
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},
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"selection_filter": {
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"dimensions": true,
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"footprints": true,
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"graphics": true,
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"keepouts": true,
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"lockedItems": false,
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"otherItems": true,
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"pads": true,
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"text": true,
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"tracks": true,
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"vias": true,
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"zones": true
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},
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"visible_items": [
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0,
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1,
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2,
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3,
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4,
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5,
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8,
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9,
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10,
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11,
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12,
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13,
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15,
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16,
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17,
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18,
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19,
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20,
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21,
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22,
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23,
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24,
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25,
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26,
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27,
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28,
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29,
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30,
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32,
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33,
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34,
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35,
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36,
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39,
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40
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],
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"visible_layers": "fffffff_ffffffff",
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"zone_display_mode": 0
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},
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"meta": {
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"filename": "Fireball_panel.kicad_prl",
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"version": 3
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},
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"project": {
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"files": []
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}
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}
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@ -123,8 +123,8 @@
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"min_microvia_drill": 0.09999999999999999,
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"min_resolved_spokes": 2,
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"min_silk_clearance": 0.049999999999999996,
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"min_text_height": 0.7999999999999999,
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"min_text_thickness": 0.08,
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"min_text_height": 1.0,
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"min_text_thickness": 0.153,
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"min_through_hole_diameter": 0.3,
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"min_track_width": 0.19999999999999998,
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"min_via_annular_width": 0.08,
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@ -409,7 +409,7 @@
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"pinned_symbol_libs": []
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},
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"meta": {
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"filename": "Fireball.kicad_pro",
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"filename": "Fireball_panel.kicad_pro",
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"version": 1
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},
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"net_settings": {
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@ -1,4 +1,4 @@
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20414948694444620
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20416639977451822
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Audio_Module
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Reverb_BTDR-1H
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Digital Reverberation Unit, http://www.belton.co.kr/inc/downfile.php?seq=17&file=pdf (footprint from http://www.uk-electronic.de/PDF/BTDR-1.pdf)
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@ -80486,6 +80486,13 @@ mounting hole 8.4mm no annular m8
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0
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0
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SynthMages
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6.3mm_NPTH_MAXJLCPCB
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Mounting Hole 6.4mm, no annular, M6, DIN965
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mounting hole 6.4mm no annular m6 din965
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0
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0
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0
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SynthMages
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C_Rect_L22.0mm_W6.1mm_P20mm_MKT_BIG_RED_CAP
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C, Rect series, Radial, pin pitch=22.50mm, , length*width=24*7mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf
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C Rect series Radial pin pitch 22.50mm length 24mm width 7mm Capacitor
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|
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