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|| B.Type == A.Type && A.Net != B.Net" (condition "A.Type == 'track' && B.Type == 'graphic')")) # edge clearance condition "A.Type == 'pad' && !A.isPlated()" condition "A.isPlated() && B.Type == 'track'" condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == A.Type")) # 4-layer condition "A.Type == 'via' && B.Type == 'track'" condition "A.Type == 'track' && B.Layer == 'Edge.Cuts'" condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'" condition "A.Net != B.Net" (condition "A.Type == 'via'" condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'" (condition "A.Net != B.Net" (condition "A.Type == 'via' && B.Type == 'track'" (condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net" condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'" (condition "A.Net != B.Net" (condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track'" (condition "A.Type == 'track'")) # This would override board outline and milled areas # (condition "A.Type == 'via'" (condition "A.Type == 'via' && B.Type == A.Type" condition "A.Type == 'track'" (condition "A.Type == 'via'" (condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'" (condition "A.Net != B.Net" (condition "A.Type == 'track' && B.Type == A.Type && A.Net == B.Net" condition "A.Type == 'pad' && !A.isPlated()" (condition "A.Type == 'pad' && !A.isPlated()" condition "A.isPlated() && B.Type == 'track'" condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'graphic')")) # edge clearance condition "A.Type == 'via'" condition "A.Type == 'track' && B.Type == 'track'" (condition "A.Type == 'pad' && !A.isPlated()" condition "A.isPlated() && B.Type == 'track'" (condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'" condition "A.Net != B.Net" (condition "A.Type == 'pad' && B.Type == 'graphic')")) # edge clearance condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net" condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track'" ; DRILL file {KiCad 5.1.10-88a1d61d58~90~ubuntu20.04.1} date Sat Aug 7 13:40:31 2021 ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole Total plated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes are merged with plated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/DIP-14_W7.62mm_Socket_LongPads.kicad_mod Normal file View File Schematics/Enlarge/Enlarge.kicad_prl Normal file View File Schematics/notes.txt.

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