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BackReport for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 Not plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole Total plated holes Total unplated holes count 16 Not plated through holes are merged with plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole T3.
- 9.198972e+01 1.055000e+01 facet normal -0.55474 0.0546157 0.830229.
- 0.00987306 0.9884 vertex 5.2649.
- 2.90049 -0.00317369 18.9333 facet normal 0.18301 -0.98059 0.0703589.