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Per feed. The file will get big, but whatever. Button color, image location KiCad 6, update symbols Hardware/PCB/precadsr/potsetc.kicad_sch | 1960 Hardware/PCB/precadsr/potsetc.sch | 602 Hardware/PCB/precadsr/precadsr.cmp | 45 .../fastestenv_Jack_Hole.kicad_mod | 17 .../Kosmo_LED_Hole_NPTH.kicad_mod | 17 .../precadsr_panel_al/precadsr_panel_al.sch | 264 .../Panel/precadsr_panel_al/sym-lib-table | 4 README.md | 8 "active_layer_preset": "All Layers", "active_layer_preset": "All Copper Layers", re-re-remove the mysterious extra trace 5040873587dbb57684343269abab88d35cf7124b Update Schematics/schematic_bugs_v1.md Update Schematics/schematic_bugs_v1.md Clock POT is too small for film; is film needed? - Smaller cap (476nF?) for C1 Ceramic 104s for C10, C14, might be more robust and easier to use) and adjust the placement sphere_starting_rotation = 90; // for inset labels, translating to this height controls label depth label_inset_height = thickness-1; STLs, 10hp version, others schematics More experimentation with panel alignment before printing 9a2ab6dc7f initial notes for v1 build Schematics/bad_trace_v1.jpeg Normal file View File Align panel to integer pseudo-origin, remove testing text, decrease title label font so we don't lose it bd1352a047 Fix annoyance of 2x05 IDC header triangle being so far out ...Header_2x05_P2.54mm_Vertical_Fixed_Ground_Fill.kicad_mod | 6 .../Jack_6.35mm_PJ_629HAN.kicad_mod | 34 ...0D_Single_Vertical_CircularHoles.kicad_mod | 41 .../PinHeader_1x10_P2.54mm_Vertical.kicad_mod .

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