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Report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes Total unplated holes count 0 Minor layout tweaks merged pull request 'new_footprints' (#5) from new_footprints into main pull from: pcb_finalization merge into.

• R26 - D36/R47 too close .
• Module lora lorawan Multiprotocol radio SoC module https://www.raytac.com/download/index.php?index_id=43.
• 1.989125e+000 2.470218e+001 facet normal -0.439084 0.687856 0.577979.
• Polyhedron height, * Knurled.
• X="4.6" y="3.2"/> New Pull Request

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