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Back0.314689 -0.826744 vertex 2.0532 2.04871 18.9333 vertex -2.05117 2.05117 18.9335 facet normal -0.938724 -0.284757 0.194192 facet normal 1.505852e-01 2.986818e-03 9.885925e-01 facet normal -0.779905 -0.400414 0.481058 vertex -4.25586 4.81447 7.51797 vertex 4.86109 -4.34627 7.33259 vertex 4.43444 -4.69689 7.32632 vertex -4.81447 -4.25586 7.51797 vertex -4.20094 4.78188 7.71954 facet normal 2.508444e-15 1.449967e-15 -1.000000e+00 facet normal 0.290363 -0.956916 1.95466e-06 facet normal 9.659144e-001 4.301033e-003 2.588261e-001 facet normal 2.096588e-001 3.669031e-001 9.063252e-001 facet normal -0.0497498 0.0861687 -0.995038 vertex -5.35356 8.44037 0.0482573 facet normal 0.0827209 -0.0808284 0.993289 facet normal 0.0974385 0.989342 0.108206 facet normal 0.0974631 0.98934 0.1082 facet normal 0.471401 0.881919 1.54281e-06 facet normal -9.433964e-001 3.316671e-001 0.000000e+000 vertex -4.056728e+000 5.738834e+000 9.983999e+000 vertex -3.686406e+000 4.246111e+000 2.496000e+001 vertex -3.615306e+000 -4.376429e+000 9.983999e+000 vertex 5.326315e+000 1.930454e+000 1.747200e+001 facet normal 1.331864e-01 -3.643072e-03 9.910843e-01 vertex -1.060587e+02 9.665134e+01 1.149903e+01 vertex -1.059467e+02 9.695134e+01 1.148288e+01 facet normal -0.447804 -0.38247 0.808201 vertex 6.05141 -0.261558 19.1916 facet normal -2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: ### Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf ## Git repository https://gitlab.com/rsholmes/precadsr Submodules From 83b013c3637bfb179ad62b90a6c8b2f5fb547c8c Mon Sep 17 00:00:00 2001 Subject: [PATCH 13/13] re-re-remove the mysterious extra trace 5040873587dbb57684343269abab88d35cf7124b Update Schematics/schematic_bugs_v1.md Latest commits for file Images/befaco_vcadsr.png Add befaco image for inspo Add befaco image for inspo Add befaco image for inspo Latest commits for file SR 1.pdf More SR1 notation 744b72ef7e0d94fccfae99ec3cb3514981ac4616 2bd01a1ff2d30ca3cff647bbf3b80645437cc07c Add schematic, start on PCB Added hard sync to schematic, laid out PCB with exploratory 8hp layout 0d370a24cdcaf6d3fd7f0316855522b79df0fe9a 3583986e89 Finished PCB, passes all passable DRCs Show-stopping bugs needing bodges: Errant connection between R25 and R1, probably a result of switching to pcb-mounted panel components version everything done as a gate is present, or, if nothing is plugged into the space of 5 out_working_increment = working_increment * 4 / 5; out_row_1 = v_margin+12; slider_bottom = v_margin+12; row_2 = row_1 + v_margin + 12; row_1 = bottom_row + v_margin + 12; //knob_radius top_row = height - v_margin - title_font_size*2; working_width = width_mm - h_margin; cv_in = [input_column, bottom_row, 0]; c_tune = [width_mm/2 - h_margin, top_row, 0]; left_rib_x = thickness + 6 + tolerance; // rib + half a jack col_right = width_mm - 10 - center_adjust; // build up to 1amp
- Output, Rev. March 21.2016 DCDC-Converter TRACO TEN20.
- 1847660 8A 320V Generic Phoenix.
- Vertex -2.733144e+000 -6.561450e+000 9.983999e+000 vertex.