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LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes Total unplated holes count 16 ============================================================= Total unplated holes count 16 ============================================================= Total unplated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/SOT-23_Handsoldering.kicad_mod Normal file View File 3D Printing/AD&D 1e spell names rendered as raster using Filmoscope Quentin Normal file View File Synth_Manuals/LABOR_MANUAL.pdf Normal file Unescape Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 L1 : F.Cu front L2.

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