Labels Milestones
BackHttp://www.st.com/resource/en/datasheet/stm32l476me.pdf WLCSP-81, 9x9 raster, 4x4mm package, pitch 0.4mm; see section 7.1 of http://www.st.com/resource/en/datasheet/stm32f051t8.pdf UFBGA-100, 12x12 raster, 7x7mm package, pitch 0.8mm; see section 7.4 of http://www.st.com/resource/en/datasheet/stm32f071v8.pdf WLCSP-63, 7x9 raster, 3.228x4.164mm package, pitch 0.4mm; see section 7.6 of http://www.st.com/resource/en/datasheet/stm32f446ze.pdf UFBGA-144, 12x12 raster, 7x7mm package, pitch 0.5mm; see section 7.1 of http://www.st.com/resource/en/datasheet/DM00282249.pdf WLCSP-90, 10x9 raster, 4.223x3.969mm package, pitch 0.4mm; see section 6.3 of http://www.st.com/resource/en/datasheet/stm32f103ze.pdf Lattice caBGA-381 footprint for ECP5 FPGAs, based on the streets of the rail + a safety margin // Width of module (HP width = 36; // [1:1:84] /* [Holes] */ hole_dist_top = 2.5; //mm first_col = 10.1+center_adjust; //mm second_col = width_mm/2; //mm third_col = 60.7-center_adjust; //mm cv_in = [h_margin, row_1, 0]; square_out = [output_column, row_2, 0]; fm_lvl = [second_col, second_row, 0]; //Third row interface placement fm_in = [first_col, fourth_row, 0]; pwm_cv_lvl = [width_mm - h_margin - working_width/8, row_4, 0]; pwm_cv_lvl = [width_mm - h_margin - working_width/8, row_2, 0]; audio_in_2 = [left_col, row_3, 0]; manual_2 = [left_col, row_2, 0]; pwm_in = [input_column - h_margin/2, row_1, 0]; pwm_in = [input_column - h_margin/2, row_1, 0]; saw_out = [output_column, row_1, 0]; pwm_in = [input_column - h_margin/2, bottom_row, 0]; fm_in = [input_column - h_margin/2, row_1.
- Vertex -5.3829 4.57828 7.06725 vertex -4.78839.
- -2.598328e-03 -9.811449e-01 vertex -1.077013e+02 9.695134e+01.
- -0.353629 0.430896 0.830226 facet.