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BackVersion *.bck New KiCad version; non Al panel Gerbers # Netlist files (exported from Eeschema # Autorouter files (exported from Eeschema *.net # Autorouter files (exported from Pcbnew # Exported BOM files *.xml *.csv # KiCad backups folders temp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) Total plated holes Total unplated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes: merged pull request 'new_footprints' (#5) from new_footprints into main 1705ad98fb Put title box in PDF export' (#4) from schematic into main 96f746fa2d Final tweaks, version submitted to JLCPCB on 20240124 3d279dd88c Finish schematic, add.
- Normal -0.956945 0.288313 0.0336363 vertex 1.05741 -7.11568.
- Connector, 64801011622 (https://katalog.we-online.com/em/datasheet/6480xx11622.pdf), generated with kicad-footprint-generator Molex MicroClasp.
- Vertex 3.481176e+000 3.944963e+000 2.491820e+001 facet normal -0.191478 0.962628.