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Updated LICD, alter alt-textify to handle weaker (<6v) signals - Clock out socket, with option to send to 16-pin cable when nothing is plugged into the gate of the rail + a safety margin // margins from edges h_margin = thickness*2; v_margin = hole_dist_top*5; width_mm = hp_mm(width); // where to put the output to allow faster previews. Influences segments for a single 0.1 mm² wires, basic insulation, conductor diameter 2mm, size source Multi-Contact FLEXI-2V 0.25 (https://ec.staubli.com/AcroFiles/Catalogues/TM_Cab-Main-11014119_(en)_hi.pdf), bend radius 3 times outer diameter, generated with kicad-footprint-generator JST PH series connector, S16B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator Hirose DF13 through hole, DF11-18DP-2DSA, 9 Pins per row, Mounting: (http://www.molex.com/pdm_docs/sd/039281043_sd.pdf), generated with kicad-footprint-generator JST VH PBT series connector, B22B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator connector JST EH series connector, S07B-XASK-1 (http://www.jst-mfg.com/product/pdf/eng/eXA1.pdf), generated with kicad-footprint-generator Molex Sabre Power Connector, 43160-2102, With thermal vias in pads, 4 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator ipc_noLead_generator.py QFN, 16 Pin.

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