Labels Milestones
BackTemp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) T5 15.200mm 0.5984" (1 hole) Total plated holes count 0 Minor layout tweaks Finish schematic, add PDF Fix for component clearance, panel thickness from printer .../luther_triangle_10hp_rib_space_fixes.stl | Bin 0 -> 23847 bytes Panels/FireballSpell_Large.webp | Bin 0 -> 31010 bytes Panels/label_test.stl | Bin 0 -> 74084 bytes Docs/precadsr_layout_front.pdf | Bin 0 -> 104908 bytes Panels/title_test.scad | 22 Hardware/PCB/precadsr/precadsr.sch | 412 Hardware/PCB/precadsr/precadsr.xml | 1656 create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/SolderWirePad_1x01_Drill1mm.kicad_mod create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/C_Disc_D3.0mm_W1.6mm_P2.50mm.kicad_mod delete mode 100644 Fireball/Fireball.kicad_dru create mode 100644 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr create mode 100644 3D Printing/Pot_Knobs/potentiometre_v3_1.5_merged.stl create mode 100644 Images/IMG_6777.JPG MK_VCO/Fireball/Fireball VCO saw wave core.circuitjs.txt More repo cleanup, adopt github .gitignore file f45c980890 Align panel to integer pseudo-origin, remove testing text, decrease title label font size to 9mm and align it precisely for repeatability b11a8d31874f2e074879a668b4f6eb5f32915bd6 Change transistor footprint to inline_wide, fix DRC ground plane Binary files /dev/null and b/3D.
- -0.392534 0.63508 facet normal 1.455970e-001 -2.517387e-001.
- -0.111601 -0.367723 0.923214 facet.
- 3.314095e-15 -2.123847e-15 1.000000e+00 facet normal -2.890007e-001.
- Vertex -0.162663 -6.59163 7.16505 vertex -0.319077 -6.63876.