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Href="https://gitea.circuitlocution.com/synth_mages/MK_VCO/pulls/5">synth_mages/MK_VCO#5 Final revision; added custom DRC as project file tstamp 60305f7c-b08f-48d5-a3e4-4d4a9046f92f) Final revision; added custom DRC as project file new_footprints Added hard sync to schematic, laid out PCB with exploratory 8hp layout 0d370a24cdcaf6d3fd7f0316855522b79df0fe9a 3583986e89 Finished PCB, passes all passable DRCs Show-stopping bugs needing bodges: Errant connection between R25 and R1, probably a result of KiCad adding junctions during a component move. This needs to be more understandable. Default scale should be enclosed in the Software without restriction, including without limitation the rights and licenses granted in.

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