3
1
Back

Href="https://gitea.circuitlocution.com/synth_mages/precadsr/commit/40588ba725f2f6c7240cc5d95c2a8af539e27e15">40588ba725f2f6c7240cc5d95c2a8af539e27e15 Update README.md 8be0bd80e05e7fe62720d7fda27423a4c75b90a3 Update README.md acf6d57d9f34ce2c424f4c9834d80264fa5ffd89 @circuitlocution.com renamed repository from precadsrprecadsr to synth_mages/precadsr 2a5bb74bbd Stuff all teh scad files in Stuff all teh scad files in 2a5bb74bbd0830b4c30d8004e4cdd9ae79e21770 Update Schematics/schematic_bugs_v1.md more fixes a5c5ff12ce18fecaaf346f973863d12bf361ac82 From 4d8e233e93a0e0142056dfcbd680a65973bd0ebb Mon Sep 17 00:00:00 2001 Subject: [PATCH 07/13] Update Schematics/schematic_bugs_v1.md Clock POT is the decade counter expects CLOCK to pass 1/2 of V+ (i.e. 6v) but many external clock sources cycle between 0v and 5v max // gate out (j4/j10) // clock out (j5/j12) // glide in (sleeve and normal both GND 6x Sockets, 2pin: Gate out (could normal to TP10, optional) - Casc Out normal to TP10, optional 2x Toggle Switches, 2pin: - reset in - pause in - CLOCK out - could be shortened a bit 057198b8de MK VCO and Luthers Update README.md 83b013c3637bfb179ad62b90a6c8b2f5fb547c8c Update README.md 40588ba725f2f6c7240cc5d95c2a8af539e27e15 Update README.md c9e81f0cc630cea052574ce7c50b3e82145bb626 Image of caxia score d952ec97f3d5e1172c33dcefe438ee5d18f8d87d Start of LM13700 version to see why main *-backups Forget (and ignore) fp-info-cache file as it is machine-specific data Merge pull request 'new_footprints' (#5) from new_footprints into main Reviewed-on: https://gitea.circuitlocution.com/synth_mages/MK_VCO/pulls/4 Put title box in PDF export 45cf8c00cd Merge pull request synth_mages/MK_SEQ#2 b77534e3fc Added schmancy pcb for v1 front panel design and includes 2.5mm centerward shift for input and output jacks Latest commits for file Synth Mages Power Word Stun Panel.kicad_prl 78 lines { "board": { updates to rev 2 Notes on needed revisions from revision 1: Fix silkscreen.

New Pull Request