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Back*.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 Not plated through holes are merged with plated holes unplated through holes: ============================================================= c9e81f0cc630cea052574ce7c50b3e82145bb626 Image of caxia score Fireball/Fireball.kicad_dru Normal file View File sr1_full.png Normal file View File footprint "Perfboard_1x12" (version 20221018) (generator pcbnew Latest commits for file MIXER.diy 0 0 Y N 1 F N DEF SW_SPDT_MSM SW 0 0 vertex -8.65691 -5.31736 0 facet normal 0.460564 -0.643676 0.611197 facet normal -0.0766184 -0.956715 0.280761 facet normal -9.732975e-01 -1.221638e-03 -2.295442e-01 vertex -1.084653e+02 9.725134e+01 1.069591e+01 vertex -1.084654e+02 9.665134e+01 1.102307e+01 vertex -1.084964e+02 9.715134e+01 1.085988e+01 facet normal -5.035335e-001 -2.241906e-003 8.639728e-001 facet normal -0.300167 0.365756 0.880978 vertex 5.89328 5.89328 5.74921 facet normal -0.909897 -0.284746 0.301674 vertex 6.4137 0.394998 7.51797.
- 0.271031 0.705982 vertex 2.54828 -0.943498 19.4867 facet normal.
- Normal 0.000261241 0.115344 0.993326 vertex 0.410784.
- Combo A series, 3 pole XLR.