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BackDrill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes unplated through holes: unplated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00.
- LFCSP, exposed pad, 7x7mm body (http://www.analog.com/media/en/technical-documentation/data-sheets/AD7951.pdf.
- 26.0mm width 5.0mm Capacitor C, Rect.
- Normal 0.54795 -0.364881 0.752737 facet normal 0.81598.
- 2.593993e-001 -4.439972e-001 8.576587e-001 facet normal -8.334678e-001.
- Vertex 2.10997 8.94883 7.89406.