Apply jlcpcb's design rules, small fixes for those

This commit is contained in:
George Dorn 2023-07-26 20:18:47 -07:00
parent 7022ad9ddb
commit 19116ba39d
3 changed files with 443 additions and 438 deletions

View file

@ -103,17 +103,17 @@
"allow_blind_buried_vias": false,
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.0,
"min_clearance": 0.19999999999999998,
"min_copper_edge_clearance": 0.0,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_silk_clearance": 0.0,
"min_silk_clearance": 0.049999999999999996,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.19999999999999998,
"min_via_annular_width": 0.049999999999999996,
"min_via_diameter": 0.39999999999999997,
"min_via_annular_width": 0.08,
"min_via_diameter": 0.44999999999999996,
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0,
"use_height_for_length_calcs": true