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FPGA Maxim WLP-12, W121H2+1, 2.008x1.608mm, 12 Ball, 4x3 Layout, 0.4mm Pitch, https://www.nxp.com/docs/en/package-information/SOT1963-1.pdf ST LFBGA-354, 16.0x16.0mm, 354 Ball, 19x19 Layout, 0.8mm Pitch, https://www.micron.com/-/media/client/global/documents/products/data-sheet/dram/ddr3/4gb_ddr3l.pdf#page=25 FBGA-78, 10.5x9.0mm, 78 Ball, 9x13 Layout, 0.8mm Pitch, https://www.ti.com/lit/ml/mpbg777/mpbg777.pdf BGA 289 0.8 ZAV S-PBGA-N289 Texas Instruments, DSBGA, area grid, NSMD pad definition (http://www.ti.com/lit/ds/symlink/tlv320aic23b.pdf, http://www.ti.com/lit/wp/ssyz015b/ssyz015b.pdf Texas Instruments, DSBGA, area grid, YBG pad definition, 0.95x1.488mm, 6 Ball, 2x3 Layout, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32g031y8.pdf ST WLCSP-20, ST die ID 461, 4.63x4.15mm, 115 Ball, X-staggered 18x10 Layout, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32g051f8.pdf#page=102 ST WLCSP-25, ST die ID 494, 3.3x3.38mm, 49 Ball, 7x7 Layout, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32l496wg.pdf ST WLCSP-132, ST die ID 450, 4.96x4.64mm, 156 Ball, 13x12 Layout, 0.35mm Pitch, https://www.st.com/resource/en/datasheet/stm32h747xi.pdf DFN, 6 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-dfn/(DCB6)%20DFN%2005-08-1715%20Rev%20A.pdf), generated with kicad-footprint-generator Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-113-02-xx-DV-TE, 13 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator Molex Mini-Fit Sr. Power Connectors, old mpn/engineering number: 1-794107-x, 11 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator Soldered wire connection, for 4 times 0.25 mm² wires, reinforced insulation, conductor diameter 0.65mm, outer diameter 1mm, size source Multi-Contact FLEXI-xV 2.0 (https://ec.staubli.com/AcroFiles/Catalogues/TM_Cab-Main-11014119_(en)_hi.pdf), bend radius 3 times outer diameter, generated with kicad-footprint-generator Molex Nano-Fit Power Connectors, 43915-xx10, With thermal vias in pads, 4 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0834-6-81&productname=DF12E(3.0)-50DP-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000992393), generated with kicad-footprint-generator ipc_noLead_generator.py QFN, 16 Pin package with 1.27mm pin pitch, compatible with SOIC-8, 3.9x4.9mm body, exposed pad, 4x4mm body, pitch 0.5mm UFBGA-64, 8x8 raster, 3.347x3.585mm package, pitch 0.65mm UFBGA-32, 6x6, 4x4mm package, pitch 0.4mm; see section 7.4 of http://www.st.com/resource/en/datasheet/stm32f302vc.pdf WLCSP-100, 10x10 raster, 8x8mm package, 0.5mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=266, NSMD pad definition Appendix A BGA 484 0.8 SBG485 SBV485 LFCSP, exposed pad, thermal vias, http://www.ti.com/lit/ds/symlink/drv8870.pdf 20-Pin Thermally Enhanced Thin Shrink Small Outline (SS)-5.30 mm Body [SSOP] (see Microchip Packaging Specification 00000049BS.pdf SSOP28: plastic shrink small outline package; 16 leads; body width 4.4 mm; Exposed Pad Variation BB; (see Linear Technology 05081955_0_DHC18.pdf DHD Package; 16-Lead Plastic HTSSOP (4.4x5x1.2mm); Thermal pad with vias; (http://www.ti.com/lit/ds/symlink/drv8800.pdf HTSSOP, 16 Pin (https://www.ti.com/lit/ds/symlink/tpa6132a2.pdf#page=24), generated with kicad-footprint-generator Soldered wire connection, for a single 0.75 mm².

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