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X="2.4" y="3.6"/> Update luther's layout Update luther's layout Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) Total plated holes count 16 Not plated through holes are merged with plated holes Total unplated holes count 16 Not plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969.

-6.296935e-01 3.190811e-04 vertex -1.030956e+02 9.452922e+01 4.255000e+01 facet.
Sot487-1_po.pdf HTSSOP, 38 Pin (JEDEC.
(http://ww1.microchip.com/downloads/en/DeviceDoc/mic5353.pdf), generated with kicad-footprint-generator Molex KK-254 Interconnect.
0.915279 -0.396628 0.0703596 facet normal -0.645449 -0.129422 0.752759.

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