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BackHardware/PCB/precadsr_Gerbers/precadsr-NPTH.drl create mode 100644 Panels/Futura XBlk BT.ttf and /dev/null differ main synth_tools/Schematics/SynthMages.pretty/PinSocket_1x02_P2.54mm_Vertical.kicad_mod 42 lines synth_tools/PCB Notes.txt 17 lines Notes from debugging Clock POT is too small; need more than fifty percent (50%) of the License, but not also under the MIT License (MIT) Copyright (c) 2013 Julian Gruber
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