Labels Milestones
BackPlanes where convenient. Hardware/PCB/precadsr/potsetc.kicad_sch Normal file View File https://youtu.be/v9A9n-kMjz0?t=209 (until ~4:30 New: A different Timbalada https://youtu.be/frLXzG9-W3Q?t=955 From a840574ffb1f388603595f7bc07f1297bb707d9a Mon Sep 17 00:00:00 2001 Subject: [PATCH] Apply jlcpcb's design rules, small fixes for those couple more minor clearance tweaks Add ground fills, fix some clearance issues, add PCB slot, more options for potentiometer spoke placement Fix rail clearance issues, make all power traces large "rules": { PCB initial layout, no traces PCB initial layout, no traces "solder_mask_clearance": 0.0, PCB initial layout, no traces "silk_line_width": 0.15, PCB initial layout, no traces "silk_line_width": 0.15, "silk_text_italic": false, "silk_text_size_h": 1.0, "silk_text_size_v": 1.0, "silk_text_thickness": 0.15, "silk_text_upright": false, "zones": { "min_clearance": 0.5 } }, updates to rev 2 beta revised README.md to rev 2 beta by adding +5V, and both trigger/gate and CV routing updates led holes to PCB edge 4.9399999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf 37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, distance of mounting holes to 5mm + unplated, and revises jack footprint ) (polygon (pts updates to rev 2 's notes on updating the fireball for rev 2 's notes on repique/caixa, two or three for surdos