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Back65 lines # Temporary files *.000 *.bak *.bck *.zip *.DS_Store *~ .gitignore-extra *.dsn *.kicad_pcb-bak *.kicad_sch-bak *-backups */fp-info-cache *.kicad_prl *.sch-bak *~ _autosave-* *.tmp *-save.pro *-save.kicad_pcb fp-info-cache # Netlist files (exported from Eeschema *.csv *.lck ########################## # Additional ignored # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1.
- -4.908041e-01 -3.188436e-04 vertex -9.121820e+01.
- Normal 0.706045 0.0555529 0.705985.
- Nichicon, 4.0x5.4mm SMD capacitor, aluminum.
- -0.124716 -0.987214 0.0992685 facet normal.
- 2.84551 18.8953 facet normal -0.277896 -0.916106.