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File Schematics/SynthMages.pretty/Perfboard_1x12.kicad_mod # Temporary files *.000 *.bak *.bck *.zip *.DS_Store *~ .gitignore-extra *.dsn *.kicad_pcb-bak *.kicad_sch-bak *-backups *.kicad_prl *.sch-bak *~ _autosave-* *.tmp *-save.pro *-save.kicad_pcb fp-info-cache *.lck # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: unplated through holes: unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes count 16 Latest commits for file PSU/psu.diy Add PSU Latest commits for file Schematics/Dual_VCA_with_cv2.diy Add radio shaek with cv2 version Add html test version facet normal -0.768293 -0.629624 0.115323 facet normal -0.478838 0.872279 0.0992143 facet normal 0.292532 0.954697 0.0545798 facet normal 4.657735e-001 8.129458e-001 3.495341e-001 vertex -3.410179e+000 -2.719732e+000 2.475471e+001 facet normal 0.617515 -0.144952 0.773087 facet normal 5.212690e-001 8.533924e-001 0.000000e+000 facet normal -0.768414 0.630746 0.108161 facet normal -4.084288e-01 -9.127902e-01 0.000000e+00 vertex -1.038646e+02 9.578044e+01 2.655000e+01 facet normal -7.814949e-16 -4.641879e-15 1.000000e+00 facet normal -0.135117 0.297038 0.945258 facet normal -4.496502e-001 -7.868875e-001 4.226378e-001 vertex 7.506481e-001 5.373734e+000 2.480400e+001 facet normal 0.881906 -0.471425 3.5557e-06 facet normal -0.0808315 0.0820554 0.993344 vertex 4.10946 -5.18289 7.85151 vertex 6.56738 -0.762348 7.85113 facet normal -5.804319e-01 2.431244e-03 -8.143051e-01 facet normal -0.124717 -0.987204 0.0993674 facet normal -9.013511e-01 1.491429e-03 4.330867e-01 vertex -1.084402e+02 9.665134e+01 1.109822e+01 vertex -1.084398e+02 9.725134e+01 1.062078e+01 facet normal.

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