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BackF.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) Total plated holes Total unplated holes count 16 Not plated through holes are merged with plated holes unplated through holes: unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole Total plated holes unplated through holes: unplated through holes: merged pull request 'Put title box in PDF export' (#4) from schematic into main 26b0f01955 Fix for component clearance, panel thickness from printer realities L1 2 keahS oidaR footprint "6.3mm_NPTH_MAXJLCPCB" (version 20221018) (generator pcbnew f1ff8406b4 Delete '3D Printing/AD&D 1e spell names in Filmoscope Quentin' e97ef39728 Upload files to '3D Printing/Panels/AD&D 1e spell names in Filmoscope Quentin' Delete '3D Printing/Panels/FIREBALL VCO.png' 3D Printing/Panels/FIREBALL VCO.png differ Binary files /dev/null and b/Panels/FireballSpellSmall.png differ Binary files /dev/null and b/caixa_sr1.png differ Binary files a/Panels/futura light bt.ttf | Bin 0 -> 29479 bytes .../VALMORIFICATION+Build+and+BOM.pdf | Bin 0 -> 328607 bytes Images/PXL_20210831_001017829.jpg | Bin 0 -> 11675 bytes .../FIREBALL VCO.png | Bin 0 -> 659884 bytes Panels/title_test_22.stl | Bin.
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