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Close Testing before powering up: Clock In Normal - 1k to U2-8 (AND NOT short to U2-10 - Clock In Normal - 1k to U2-8 (AND NOT short to U2-10 Clock Rate - variable resist +6k between U2-8 and U2-9 Reset Sw - when two traces cross on opposite sides of the rail + a safety margin // margins from edges v_margin = hole_dist_top*2 + thickness; v_margin = hole_dist_top*2; output_column = width_mm - col_right + tolerance*4; // column from edge plus hole radius //calculated x value of exact middle of panel after deducting left/right sub-panels slider_center = (width_mm - left_panel_width - right_panel_width)/2 + left_panel_width; slider_bottom = v_margin+12; row_2 = row_1 + vertical_space/7; row_4 = row_3 + vertical_space/7; row_6 = row_5 + vertical_space/7; cv_in_1a = [left_col, row_5, 0]; audio_out_1 = [right_col, row_2, 0]; cv_2b_atten = [right_col, row_1.

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