Labels Milestones
BackMK_VCO/Panels/FireballSpell_Large_bw.png.svg 58 lines # Temporary files fp-info-cache # Autorouter files (exported from Eeschema *.csv *.lck ########################## # Additional ignored # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole Total plated holes count 16 Not plated through holes are merged.
- Thin SMD package; 3 leads; body.
- 2.964444e-001 9.550501e-001 -0.000000e+000 vertex 3.541821e+000 4.395136e+000 9.983999e+000.
- -1.165386e-14 facet normal 0.0100577 0.00636613 0.999929 vertex -7.01486.
- 9.445800e-15 facet normal 3.694683e-15 -4.689871e-15 1.000000e+00.
- The courts of a jurisdiction.