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Back"Layer B.SilkS" ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4.
- Normal 0.439079 -0.687862 0.577975 vertex -4.43088 5.75031.
- Lead Plastic Package OnSemi CASE 100CY, light-direction.
- Work is released into the public.
- 0.993323 vertex -6.43421 -0.598972 7.83559.