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Back06eccf7d9c703f23c204313298619b9281db47b3 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Add notes about wiring SW15 cross-board 9360e76802 Add design rules for jlcpcb Add some perfboard sections, power headers, teardrops From 9e7b04561b8893062b3378503805ddd100c7260f Mon Sep 17 00:00:00 2001 Subject: [PATCH] Update Schematics/schematic_bugs_v1.md Clock POT is too small for film; is film needed? From cb59d1e9c06865f5bebe8c7ee0afa4859e0766b2 Mon Sep 17 00:00:00 2001 Subject: [PATCH 03/13] More assembly notes cb59d1e9c06865f5bebe8c7ee0afa4859e0766b2 Update Schematics/schematic_bugs_v1.md Schematics/schematic_bugs_v1.md | 1.
- Use THT electrolytics, finish SMT layout.
- Normal 9.013770e-01 2.530432e-03 4.330278e-01 vertex -1.092681e+02.
- Pads Relau SPST Potter&Brumfield T9AP1D52.