Labels Milestones
BackBread 2015-10-14 16:26:40 -07:00 f80e4975fb checkpoint before getting really weird with WireIt A couple more minor clearance tweaks 9e7b04561b Add ground fills, fix some clearance issues, make all power traces large "rules": { PCB initial layout, no traces "silk_line_width": 0.15, PCB initial layout, no traces Initial kicad, images, gitignore for kicad backups .gitignore | 65 Hardware/PCB/precadsr/precadsr.kicad_pro | 471 .../precadsr-panel-Gerbers/drill_report.rpt | 26 .../precadsr-panel-CmtUser.gbr | 209 .../precadsr-panel-CuBottom.gbl | 970 .../precadsr-panel-CuTop.gtl | 970 .../precadsr-panel-CuTop.gtl | 970 .../precadsr-panel-EdgeCuts.gm1.
- 6.03331 vertex 4.74434 -8.21743 6.17306.
- CA6-VSMD Potentiometer, vertical, ACP CA14-VSMD, http://www.acptechnologies.com/wp-content/uploads/2017/10/03-ACP-CA14-CE14.pdf Potentiometer.
- Capacitor, aluminium electrolytic, 3x5.3, Cornell Dubilier Electronics SMD.
- 10mm CopperTop Type 2 Gauge, Massstab.
- 0.937985 facet normal 0.0816517 -0.0813929 0.993332 vertex -4.29176.