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2.856654e+000 2.479508e+001 facet normal -4.566403e-001 7.828531e-001 4.226355e-001 facet normal 9.085721e-01 4.177281e-01 2.038530e-04 vertex -9.093526e+01 1.020864e+02 4.255000e+01 facet normal 9.901787e-01 1.398071e-01 -2.506079e-04 facet normal -0.976251 0.0961519 0.194137 facet normal 0.07297 -0.0676954 0.995034 vertex 0.505698 -7.98874 19.9508 vertex 0.703367 9.38579 20.0916 facet normal 0.0393352 -0.305328 0.951435 facet normal 0.586516 0.714676 0.3811 facet normal 2.999145e-001 -5.145734e-001 8.032842e-001 facet normal 7.640264e-01 6.451849e-01 -1.719442e-04 facet normal -0.796858 -0.241725 0.553703 facet normal 4.729960e-001 -8.087680e-001 3.495271e-001 vertex -3.433966e+000 2.622613e+000 2.475471e+001 facet normal 4.840240e-001 -8.306754e-001 2.751348e-001 vertex -4.022055e+000 2.274596e+000 2.473857e+001 facet normal -0.282966 0.360203 0.888923 facet normal 0.780815 -0.129484 0.611197 vertex 5.40904 4.29047 7.37319 facet normal -0.133707 0.0819149 0.98763 facet normal 9.094768e-001 4.157546e-001 -0.000000e+000 vertex 5.430013e+000 4.519711e+000 2.496000e+001 vertex 6.948225e+000 1.404741e+000 9.983999e+000 vertex -3.465548e+000 6.113461e+000 9.983999e+000 vertex -4.337701e+000 5.530056e+000 1.747200e+001 facet normal -0.0376662 0.382433 0.923215 vertex -9.12468 0.183929 3.76384 facet normal -0.0916557 -0.0110255 0.99573 facet normal 4.648440e-001 8.134776e-001 3.495343e-001 facet normal 0.15129 0.0100873 0.988438 facet normal -0.061823 0.114014 0.991554 facet normal -0.114495 0.30557 0.945261 facet normal 0.00906568 -0.644985 0.764141 facet normal 0.115076 -0.00068584 0.993356 facet normal -3.609433e-15 -2.925733e-15 1.000000e+00 facet normal 0.954697 0.292532 0.0545798 facet normal -0.0816193 0.828696 0.553715 vertex 0.301613 9.71631 3.26879 facet normal 7.614451e-01 5.127838e-01 3.965528e-01 vertex -1.095272e+02 9.965134e+01 1.755000e+01 facet normal -0.401177 0.913294 0.07036 vertex 3.43863 8.76148 20.0916 vertex -1.77842 7.79176 19.9496 facet normal -2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf) * [BOM](Docs/precadsr_bom.md) * [Build notes](Docs/build.md ## GitHub repository ## Git repository From 40ce306867b3d353457e134a232ee65f5767bece Mon Sep 17 00:00:00 2001 Subject: [PATCH] edits README.md file 4f6e9e0984 Updated LICD, alter alt-textify to handle weaker (<6v) signals Clock out socket, with option to send to 16-pin cable when nothing is plugged into the gate input, indefinitely. This can be reasonably considered independent and separate.

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