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Variation; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot371-1_po.pdf STC SOP, 16 Pin (https://www.stcmicro.com/datasheet/STC15F2K60S2-en.pdf#page=156), generated with kicad-footprint-generator ipc_noLead_generator.py Nexperia wafer level chip-size package; 15 bumps (6-3-6), 2.37x1.17mm, 15 Ball, 6x3 Layout, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32g431c6.pdf ST WLCSP-49, ST die ID 468, 3.15x3.13mm, 49 Ball, 7x7 Layout, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32wb15cc.pdf#page=119 ST WLCSP-52, ST die ID 468, 3.15x3.13mm, 49 Ball, 7x7 Layout, 0.4mm Pitch, YFF0006, NSMD pad definition Appendix A BGA 676 1 RF676 RFG676 Artix-7 BGA, 26x26 grid, 27x27mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=275, NSMD pad definition Appendix A BGA 484 0.8 SBG485 SBV485 LFCSP, exposed pad, thermal vias, http://www.ti.com/lit/ds/symlink/drv8870.pdf 20-Pin Thermally Enhanced Thin Shrink Small Outline (SS)-5.30 mm Body [QFN]; (see Microchip Packaging Specification 00000049BS.pdf 44-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8x0.9 mm Body [QFN] with thermal pad TQFP64 7x7, 0.4P CASE 932BH (see ON Semiconductor Micro8 (Case846A-02): https://www.onsemi.com/pub/Collateral/846A-02.PDF PSOP44: plastic thin shrink small outline 7,5mm long https://toshiba.semicon-storage.com/info/docget.jsp?did=53548&prodName=TLP2770 6-Lead Plastic DFN (3mm x 2mm) (see Linear Technology DFN_32_05-08-1734.pdf DFN44 8.9x5, 0.4P; CASE 506BU-01 (see ON Semiconductor 506CN.PDF DC8 Package 8-Lead Plastic DFN (1.3mm x 1.2mm DFN, 8 Pin (https://www.ti.com/lit/ds/symlink/lp2987.pdf#page=26), generated with kicad-footprint-generator ipc_qfp_generator.py 64-Lead Plastic Thin Quad Flatpack (PF) - 14x14x1 mm Body, 2.00 mm [TQFP] (see Microchip Packaging Specification 00000049BS.pdf 44-Lead Plastic Quad Flatpack (PF) - 14x14x1 mm Body, 2.00 mm [TQFP] (see Microchip Packaging Specification 00000049BS.pdf 20-Lead.

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