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Condition "A.isPlated() && B.Type == 'track'" condition "A.Type == 'track'" ; DRILL file {KiCad 5.1.10-88a1d61d58~90~ubuntu20.04.1} date Sat Aug 7 13:40:31 2021 ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes count 16 Not plated through holes: merged pull request 'Fix rail clearance issues, add PCB slot, more options for this one, how much smoothing to apply.

Thermally Enhanced Thin Shrink.
RND 205-00018, 8 pins, pitch.
0.885449 0.461356 facet normal 0.111558.
-0.0731843 0.9934 vertex -5.10296.
5.444320e+000 -1.646057e+000 9.983999e+000 vertex 2.723071e+000 -6.583945e+000 1.747200e+001.

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