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# LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) Total plated holes count 16 Not plated through holes: merged pull request 'pcb_finalization' (#1) from bugfix/10hp into main Merge pull request synth_mages/MK_VCO#5 Merge pull request 'new_footprints' (#5) from new_footprints into main created pull request 'More schematics' (#3) from schematic by Eeschema 5.1.10-88a1d61d58~90~ubuntu20.04.1 Component Count: 77 Refs 3 pin Molex connector 2.54 mm spacing 3 pin Molex header 2.54 mm spacing"/>

Photodiodes, https://www.thorlabs.de/drawings/374b6862eb3b5a04-9360B5F6-5056-2306-D912111C06C3F830/FDGA05-SpecSheet.pdf TO-92 leads.
-0.826242 vertex 2.68773 -1.08464 18.9318.
Normal -0.533415 0.16181 0.830233 vertex -8.44684 3.49879 3.76384.
= knob_radius_bottom*-1; // this is good.
Header, 1x04, 2.54mm pitch, DIN 41651 / IEC.

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