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Back# Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) Total plated holes count 16 Not plated through holes are merged with plated holes Total unplated holes count 16 Not plated through holes: unplated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Delete 'Panels/futura medium bt.ttf' Panels/futura medium bt.ttf From 303a55e23667987c98f6d6f4be567bff3180e8cb Mon Sep 17 00:00:00 2001 Subject: [PATCH] Documentation, some cosmetic sh/PCB updates Docs/precadsr.pdf | Bin 0 -> 71984 bytes 3D Printing/Panels/image.png | Bin 0 -> 71984 bytes 3D Printing/Panels/MAGIC MISSILE VCF.png' Delete '3D Printing/AD&D 1e spell names in Filmoscope Quentin/Panels/PRISMATIC SPHERE.png' Delete '3D Printing/AD&D 1e spell names in Filmoscope Quentin/Panels/COLOR SPRAY.png differ Binary files a/caixa_sr2.png and b/caixa_sr2.png differ From 2537badf2888da8d57706bf8be36ba8f10d4993a Mon Sep 17 00:00:00 2001 Subject: [PATCH] To GitLab Hardware/PCB/precadsr/precadsr.kicad_pcb | 3 Hardware/Panel/precadsr-panel/fp-lib-table .
- Vishay 1012, 10.0x12.5mm, http://www.vishay.com/docs/28395/150crz.pdf SMD.
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