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Thermal vias (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-12-9/ Infineon PG-DSO 12 pin, exposed pad, thermal vias, http://www.ti.com/lit/ds/symlink/drv8870.pdf 20-Pin Thermally Enhanced Thin Shrink Small Outline (SSO/Stretched SO), see https://www.vishay.com/docs/83831/lh1533ab.pdf SSO Stretched SO SOIC 2.54 8-Lead Plastic Dual Flat, No Lead Package (JQ) - 4x4x0.5 mm Body [DFN] (see Microchip Packaging Specification 00000049BS.pdf QFN, 64 Pin (https://www.nxp.com/files-static/shared/doc/package_info/98ARH98426A.pdf), generated with kicad-footprint-generator JST EH series connector, 502386-0870 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator Samtec HLE .100" Tiger Beam.

| Pin header 2.54 mm spacing 2.
Stun.kicad_sch From 085327769df1923053fc21adb0ef584f908b8264 Mon Sep 17.

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