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BackPrinting/Pot_Knobs/10mm_potentiometer_tool.stl Executable file View File 3D Printing/Pot_Knobs/Pot2.STL Executable file Unescape Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole Total plated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes are merged with plated holes count 16 ============================================================= Total unplated holes count 0 Minor layout tweaks Finish schematic, add PDF Features already done: - Internal clock with manual control. - Clock rate goes down when resistance goes up, opposite to expectation. Glide fix - CV out, with probably +12v gates. Variable step count, 1-10 steps possible (with.
- 2.730491e+000 3.060683e+000 2.475471e+001 facet.
- 9.342550e-01 -3.566057e-01 0.000000e+00 vertex.
- -3.36088 0.18985 facet normal.