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97a7a0b59762910e1238688f287f725f632d4e8f Mon Sep 17 00:00:00 2001 Subject: [PATCH] Update luther's layout Update luther's layout Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= 0d3d72c49e606725216a5a9a4217e6c039d5a574 4675f71e05fc19d3608ee6e5061bbe79ae432fb7 c4e1c30b9b Add jlc constraints DRC; replace order number text Compare 19 commits » created pull.

Vertex 5.021640e+000 -2.681558e+000 9.983999e+000 vertex 1.107587e+000.
And 2 connected via insulated.
9.695134e+01 4.955409e+00 facet normal.

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