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Of caxia score Image of caxia score Image of caxia score Image of caxia score Samurai Latest commits for file caixa_sr1.png Image of caxia score Samurai Latest commits for file Schematics/SynthMages.pretty/Perfboard_3x12.kicad_mod PSU/Synth Mages Power Word Stun.kicad_prl Normal file Unescape Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole Total plated holes count 16 Not plated through holes are merged with plated holes Total unplated holes count 16 Not plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes unplated through holes: ============================================================= 4675f71e05fc19d3608ee6e5061bbe79ae432fb7 c4e1c30b9b Add jlc constraints DRC; replace order number text Fireball/Fireball_panel.kicad_pcb | 3 | 2_pin_Molex_header | KK254 Molex header 2.54 mm spacing Q1, Q2, Q3, Q4, Q5 R1, R2, R23, R24 | 4 | | R25, R27, R29 | 3 | 2N3904 | Small Signal NPN Transistor, TO-92 | | | S2 | 1 | B20k | Potentiometer | | Tayda | A-1624 or A-2969 | | | | | | Tayda | A-804 | | Tayda | A-1121 | | R16, R18, R26 | 3 | A1M | Potentiometer | | Tayda | A-3545, A-3489, or A-3499\*\*\* | | | | | | Tayda | A-1672.

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