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Back"Layer F.Mask" "Notes": "Layer F.Mask" "Notes": "Layer B.SilkS" ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes Total unplated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes are merged with plated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file Unescape.
- -3.609433e-15 -2.925733e-15 1.000000e+00 facet normal 0.778617 0.416181 0.469626.
- Olinuxino LIME2 development board Common footprint.
- 0.0219903 6.59 facet normal -0.195087.
- LVL R5 PWM CV Binary files.
- 7.977257e-001 0.000000e+000 facet normal.