3
1
Back

Href="https://gitea.circuitlocution.com/ /VCA/commit/0d3d72c49e606725216a5a9a4217e6c039d5a574">0d3d72c49e606725216a5a9a4217e6c039d5a574 5ff3077e8252367b7eceb0b21b0803904b695d42 d952ec97f3d5e1172c33dcefe438ee5d18f8d87d Start of LM13700 version to see why 0d3d72c49e Use THT electrolytics, finish SMT layout, try on quentin font for size Compare 2 commits » 33729ec97f More repo cleanup, adopt github .gitignore file # Temporary files *.lck # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole Total plated holes count 16 ============================================================= Total unplated holes count 0 Minor layout tweaks Finish schematic, add PDF Compare 3 commits from bugfix/v1.1 into main afea9d5a2cf23e2a33a2927086270d4d602f5a2b Final revision; added custom DRC as project.

New Pull Request