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0.119229 -0.101845 0.987629 facet normal -0.533417 -0.161807 0.830232 facet normal -6.059723e-02 5.494638e-03 9.981472e-01 vertex -1.063183e+02 9.665134e+01 8.848868e+00 vertex -1.064033e+02 9.695134e+01 8.842057e+00 vertex -1.065849e+02 9.725134e+01 8.832685e+00 facet normal -0.0817378 -0.828666 0.553744 facet normal 0.773012 -0.634392 0 facet normal 5.735729e-001 2.554278e-003 8.191506e-001 vertex -5.112638e+000 -6.441790e-002 2.488700e+001 facet normal 9.969322e-01 7.826654e-02 -6.755265e-04 vertex -1.045378e+02 9.815134e+01 1.755000e+01 facet normal -3.873393e-15 -1.000000e+00 4.657429e-14 vertex -1.065156e+02 9.725134e+01 1.020829e+01 facet normal 0.115312 -0.00018283 0.993329 vertex -6.33956 -0.410784 7.82455 vertex 6.33525 -0.41258 7.82405 facet normal 0.904824 -0.425785 0 Latest commits for branch bugfix/v1.1 Add note resulting from real TL0x4s Merge pull request 'pcb_finalization' (#1) from bugfix/10hp into main Reviewed-on: https://gitea.circuitlocution.com/synth_mages/MK_VCO/pulls/3 More schematics More experimentation with panel.

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