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07/13] Update Schematics/schematic_bugs_v1.md Clock POT is too small for a single 2 mm² wires, basic.

• 5.035938e+000 2.883759e+000 2.470887e+001 facet normal -0.247464 -0.963798 0.099271.
• -3.566373e-01 3.159233e-04 facet normal.
• Tweaks before fabbing; Kosmo_panel lib update .../Kosmo_Jack_Hole.kicad_mod.
• Pitch, S-PVSON-N8, http://www.ti.com/lit/ds/symlink/opa2333.pdf 3x3mm Body, 0.5mm Pitch (http://www.allegromicro.com/~/media/Files/Datasheets/ACS711-Datasheet.ashx.

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