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(grid_origin -1.27 106.172 (grid_origin 121.92 119.38 "Notes": "Layer F.Mask" "Notes": "Layer B.Cu" "Notes": "Layer F.Paste" "Notes": "Layer B.SilkS" ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) T5 15.200mm 0.5984" (1 hole) Total plated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes are merged with plated holes count 16 Not plated through holes are merged with plated holes count 16 Not plated through holes: unplated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 Subject: [PATCH] How to use Images/adsr.png | Bin 0 -> 30552 bytes From bada0399ca1e4fb2dd01b4ec5312596f167b34e1 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Add notes about UX component wiring 9f9f6acf76f746b4755da71c07bb656091774052 SMT updates SMT updates Checkpoint after converting most things to SMD From 054c37512afd84e9f4dd43316902a76ae73fd917 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Add a front-panel PCB "net_color_mode": 1, "opacity": { More tweaks after pro review } ], "meta": { "version": 3 }, "net_colors": null, "netclass_assignments": null, updates to rev 2 beta by adding +5V, and both trigger/gate and CV routing updates led holes to PCB edge 7.4799999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf 9-pin D-Sub connector horizontal angled 90deg THT female pitch 2.29x1.98mm mounting holes 33.3mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf 37-pin D-Sub connector horizontal.

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